1. Field of the Invention
The present invention relates to input protection circuitry for sensitive electronic circuits. More specifically, the present invention relates to the protection of integrated circuits from electrical overstress and in particular electrostatic discharge.
2. Description of the Prior Art
Integrated circuits are vulnerable to electrical overstress (EOS). EOS results from an external source discharging large transient voltages onto one or more pins of an integrated circuit. These transient voltages can include very fast transients such as those produced by an electrostatic discharge (ESD), or slower transients such as may result from powerline surges.
ESD is a well known cause of failure in integrated circuits, especially integrated circuits manufactured using CMOS processes, but also, albeit to a lesser extent, those produced by bipolar processes. In CMOS devices, the thin oxide layer of input gates cannot support high voltages without incurring damage. In bipolar devices, where the input voltage is across a junction, breakdown damage occurs when the EOS current becomes excessive.
Input protection circuits are frequently used in integrated circuits to protect against such failures. A typical input protection scheme employed is shown in schematic representation in FIG. 1. The scheme shown provides a protection circuit 2 incorporated into an integrated circuit. A similar arrangement may however be applied to the manufacture of discrete electronic devices. In the arrangement shown, a pin 1, which is used for transferring electronic signals from a main structure 3 of the integrated circuit to other electronic devices in the form of either voltages or currents, is shown connected to an ESD protection circuit 2. Although these circuits are referred to as input protection circuits, the term "input" means any electrical connection on the integrated circuit package capable of connecting the integrated circuit to external circuits. Input protection circuits are not to be understood as only protecting pins which provide the integrated circuit with input signals. Pin 1 is subsequently referred to as "the protected pin". The ESD protection circuit 2 is further connected to a voltage reference signal 4, e.g. ground, or the positive or negative voltage supply. In an integrated circuit, the protected pins are the external pins or legs of the integrated circuit package. These external pins/legs are typically connected electrically via bond wires to pads on the surface of the integrated circuit. Pads are areas of metal on the surface of the integrated circuit. Metal tracks electrically connect the pads to other parts of the integrated circuit. For input pins, the pads are typically connected to resistors which in turn are connected to the gates of MOS transistors or the bases of bipolar transistors. With output pins, the pads are typically connected to sources or drains of MOS transistors or to the collectors or emitters of bipolar transistors.
The ESD protection circuit 2 provides a low impedance path from the protected pin 1 to the ground or reference point 4 during an over-voltage event, e.g. an ESD discharge. This low impedance path minimises or eliminates damage to the integrated circuit 3. The purpose of the input protection circuit is to provide a low impedance path to ground (or indeed any arbitrary node), for discharge of any voltage transient, thus preventing damage to the integrated circuit.
Several approaches to EOS protection circuits have been developed. One approach uses diode connected devices, which may include diode connected bipolar devices having their emitter shorted to their base and diode connected MOS devices having their gate connected directly, or via a resistance, to their source. These types of devices are typically connected between each input/output pin of an integrated circuit and one or more voltage reference pins. These types of protection device restrict however input voltages to within one or two diode voltage drops of the reference voltage to which they are connected. In addition, these types of circuit are unreliable for higher levels of ESD voltages.
A further approach uses back-to-back diodes connected between each input/output pin and a reference pin. This arrangement allows input voltages to exceed the reference voltage. However, large diodes are required in order to provide effective protection at lower levels of ESD. Back-to-back diodes are unsuitable for handling higher levels of ESD.
Another approach to input protection uses Silicon Controlled Rectifier (SCR) cell structures. Protection arrangements using SCR structures are described in U.S. Pat. Nos. 5,751,525 and 4,939,616. A typical example of an SCR cell is shown in FIG. 2. The illustrated SCR cell is formed in a portion of a P-type silicon semiconductor substrate 14. It will however be immediately apparent to those experienced in the art that an N-type version of this device may also be implemented. As shown, a lightly doped N-well 15 is formed in the substrate 14. The N-well 15 has a first heavily doped region of N-type material 17 and a second heavily doped region of P-type material 16 formed in it. These two heavily doped regions 16, 17 are electrically connected to the protected pin 1 and to the circuit structure 3. A further region of heavily doped N-type material 19 is located in the P type substrate 14 at a spacing from the N-well 15. This further region 19 of heavily doped N-type material is electrically connected to ground. Alternatively, this further region of heavily doped N-type material 19 may be electrically connected to another reference potential, e.g. the positive or negative integrated circuit supply voltage. This will change the voltage at which the SCR cell will start to protect the circuit, i.e. the SCR cell's breakdown voltage.
FIG. 3 shows an equivalent electrical circuit of the structure of FIG. 2. The equivalent circuit comprises a protected pin 1 connected to the main integrated circuit structure 3. A first resistor 21 is connected between the protected pin 1 and the collector of a first transistor 26. The collector of the first transistor 26 is also connected to the base of a second transistor 22. The base of the first transistor 26 is connected to the collector of the second transistor 22. The emitter of the first transistor 26 is connected to a reference node 4 which has a reference potential, typically ground. The emitter of the second transistor 22 is connected to the integrated circuit structure 3 and to the protected pin 1. A second resistor 29 is connected between the collector of the second transistor 22 and the reference node 4. The first resistor 21 is formed by the first heavily doped N region 17 in combination with the lightly doped N-well 15. The first transistor 26 is formed by the N-well 15, the P type substrate 14 and the further heavily doped region 19 of N-type material, these forming the collector, base and emitter of the first transistor respectively. The second transistor 22 is formed by the heavily doped P-type region 16, the N-well 15 and the P-type substrate 14. The second resistor 29 is formed by the region of heavily doped N-type material 19. A typical operating characteristic for this device is shown in FIG. 4.
Normally the device operates in the high impedance region and no current flows through the protection device. However, as the voltage across the SCR cell device reaches its breakdown voltage, a phenomenon known as "avalanche conduction" occurs in the first transistor 26. Avalanche conduction occurs when a sufficiently large negative voltage is applied to a semiconductor junction, the resulting electric field pulling electrons directly out of covalent bonds. The electron-hole pairs thus created then contribute a greatly increased reverse current. This current in turn causes the first transistor 26 to start to turn on, and the voltage across its collector-emitter to drop. This region is indicated by the breakdown region in FIG. 4. As the voltage across the first transistor 26 decreases, the voltage across the first resistor 21 increases. This increase in voltage provides a biasing current for the second transistor 22. As the voltage applied to the protected pin 1 increases further, the second transistor 22 starts to switch on. As the second transistor 22 switches on, it provides a biasing current for the base of the first transistor 26, which switches the first transistor 26 on completely. This point is indicated in FIG. 4 as the "turn-on" current. At this point, the SCR device switches to a very low impedance state, indicated in FIG. 4 as the low impedance region. The protection device will remain in this low impedance state until the current drops to a level where the current flowing through the first resistor 21 is insufficient to maintain the second transistor 22 biased on. If the current being supplied to the protected pin never falls below the holding current, the SCR protection cell will remain permanently in the on state. This can happen in situations where, for example, an external driver is used which can supply more current than the holding current. This occurrence is a form of latch-up, and will prevent the integrated circuit from returning to a normal operating state after an ESD discharge.
Thus, in summary, for the typical characteristic shown in FIG. 4 for an SCR cell, under normal operating conditions the SCR cell has a high impedance state, and accordingly little current flows through the cell. When the voltage across the SCR cell exceeds what is known as the breakdown voltage, the SCR cell starts to switch on and appreciable current starts to flow. When the current increases beyond a certain limit, referred to as the "turn-on current", the SCR cell switches on completely and the SCR cell enters its low impedance region. In this region, the SCR cell allows high currents to flow without significant voltage across the terminals. Hence an SCR cell can discharge an EOS event without itself sustaining any damage.
The SCR cell remains in the "on" (low impedance) state until the current is reduced to below the value known as the holding current. At this point the cell returns to its high impedance state.
One difficulty with existing SCR cells is that they are susceptible to the phenomenon known as "latch-up". This is where an SCR cell fails to return to the high impedance state and remains in the low impedance region.
A further problem with existing SCR cells (e.g. U.S. Pat. No. 4,939,616) is that they are unipolar, and thus only suitable for protecting against unipolar ESD transients. Two SCR cells in parallel and having reversed polarities are required to provide bipolar protection. Thus, two SCR cells are required for each input/output pin on an integrated circuit. Since space is frequently at a premium on integrated circuits, this may not always be a realistic option in many instances. It is an object of the present invention to provide an SCR cell capable of effecting bipolar protection.
A further difficulty with SCR cells is that care must be taken when implementing the cells to ensure they have the correct characteristics necessary for the intended application. In particular, the breakdown voltage and holding current must be tailored to meet the application. If the breakdown voltage is too low, the cell will leak current even under normal conditions. If the holding current is too low and the circuitry in parallel with the cell (such as an external driver or internal output driver) can source a current exceeding this, then the cell may never leave its low impedance state after an ESD event. The correct characteristics may also vary from pin to pin on an integrated circuit.
The characteristics of prior art SCR cells are largely determined by the levels of doping chosen for the different regions of the SCR cell. For example, U.S. Pat. No. 4,939,616 provides an input protection device with a low trigger threshold. However, the actual characteristics of the device are defined largely by the chosen doping levels. Once a particular semiconductor manufacturing process has been selected for manufacturing an integrated circuit, the designer of the integrated circuit is limited in the changes which can be made to the SCR cell to alter its operating characteristics, e.g. after development testing. In addition, the integrated circuit designer cannot have substantially differing characteristics for different SCR cells on a single integrated circuit. It is an object of the present invention to provide an SCR cell whose characteristics may be altered without changing the manufacturing process. In particular, it is an object of the present invention to be able to readily modify the layout of a device to alter its operating characteristics.
A further problem with existing SCR cell designs is that when they are used for protecting the pins of an integrated circuit and are incorporated within the integrated circuit, the characteristics of each cell are substantially similar in terms of breakdown voltage because the characteristics of the cells are largely determined by the semiconductor manufacturing process chosen. However, the normal operating regions of each pin and their safe operating regions will vary. For example, sensitive input circuitry may require a SCR cell with a lower breakdown voltage or a lower holding current cell than output driver circuitry. It is a further object of the present invention to provide a SCR cell design such that each pin on a integrated circuit can have a different characteristic protection cell so as to maximise performance of the integrated circuit while maintaining effective ESD protection.